1. Field of the Invention
The present invention is related to a driving method, driving device and cascade source drivers for a LCD panel, and more particularly, to a driving method, driving device and cascade source drivers reducing power consumption of the LCD panel through reducing standby durations of receivers within the driving device.
2. Description of the Prior Art
With advances in resolution of a liquid crystal display (LCD), throughput between a timing controller and source drivers of a panel driving device rapidly increases, resulting in sides effects of numerous pins, additional power consumption, electromagnetic interference (EMI), etc. Thus, reduced swing differential interfaces, such as a reduced swing differential signaling (RSDS) and a mini low-voltage differential signaling (mini-LVDS), are proposed to overcome those side effects.
Please refer to FIG. 1, which is a schematic diagram of a mini-LVDS interface 100 of a conventional panel driving device. The mini-LVDS interface 100 includes a timing controller 110 and four representative source drivers 120_1-120_4 connected in series. The source drivers 120_1-120_4 respectively include receivers 130_1-130_4, converters 140_1-140_4 and transmitters 150_1-150_4.
The timing controller 110 is arranged to generate a frame signal FRM utilized for providing frame data to the source drivers 120_1-120_4. Meanwhile, the timing controller 110 further generates a system timing generation signal SYS utilized for controlling operation timings of the source drivers 120_1-120_4. The receivers 130_1-130_4 sequentially receive corresponding frame data from the frame signal FRM. The converters 140_1-140_4 respectively convert the frame data into source driving signals VS_1-VS_4. The transmitters 150_1-150_4 respectively transmit the source driving signals VS_1-VS_4 to pixel units of a LCD panel. In addition, after the receivers 130_1-130_3 complete receiving the frame data, the transmitters 150_1-150_3 respectively transmit impulse signals SP1-SP3 to the receivers 130_2-130_4 to trigger the receivers 130_2-130_4 to start the reception.
FIG. 2 is a timing diagram of signals of the mini-LVDS interface 100. Note that, the frame signal FRM includes three representative differential signals LV1, LV2, LV3 simultaneously provided to the receivers 130_1-130_4 of the source drivers 120_1-120_4. Each of the differential signals LV1, LV2, LV3 includes plural data sections DATA separated by blank sections BLK. In addition, at least one of the differential signals, e.g. the differential signal LV1, further includes reset indication sections RST, each arranged to be right after the blank section BLK synchronized with the system timing generation signal SYS, and utilized for synchronizing reception timings of the receivers 130_1-130_4 after the source drivers 120_1-120_4 are activated.
FIG. 3 is a schematic diagram of a driving process 30 of the mini-LVDS interface 100. Please simultaneously refer to from FIG. 1 to FIG. 3 to understand overall operation of the mini-LVDS interface 100. First, since the driving process 30 starts (Step 300), the timing controller 110 generates the frame signal FRM according to the system timing generation signal SYS (Step 302). Next, the source drivers 120_1-120_4 are activated to a standby state after the receivers 130_1-130_4 receives a rising impulse edge of the system timing generation signal SYS (Step 304). Later, the receivers 130_1-130_4 receive the reset indication section RST to synchronize the reception timings through activating internal reception clocks thereof (Step 306).
Since an impulse signal SP is fixed at a high level, the receiver 130_1 starts receiving the data section DATA after it receives reset indication section RST (Step 308). However, the other source drivers 120_2-120_4 remain standby since the corresponding impulses SP1, SP2, SP3 are disabled.
After the receiver 130_1 finishes the reception, the transmitter 150_1 outputs the impulse signal SP1 (Step 310) to trigger the receiver 130_2 of the next source driver 120_2 to start receiving data (Step 312). Similarly, the transmitter 150_2 outputs the impulse signal SP2 after the receiver 130_2 finishes the reception (Step 332) to trigger the next receiver 130_3 to receive data (Step 313). The transmitter 150_3 generates the impulse signal SP3 after the receiver 130_3 finishes the reception (Step 333) to trigger the next receiver 130_4 to start receiving data (Step 314), so as to complete overall data reception of an updating cycle.
At the next rising impulse edge of the system timing generation signal SYS, the converters 140_1-140_4 of the source drivers 120_1-120_4 simultaneously convert the received data section DATA into the source driving signals VS_1-VS_4 (Step 340). Finally, at a falling impulse edge of the system timing generation signal SYS, the transmitters 150_1-150_4 of the source drivers 120_1-120_4 transmit the source driving signals VS_1-VS_4 to pixel units of the LCD panel (Step 350), and the driving process 30 ends (Step 360).
To sum up, when receiving corresponding data section from the frame signal FRM, the source drivers 120_1-120_4 have to be respectively triggered by the impulse signals SP0-SP3 to start receiving data. Other than the impulse signal SP0 fixed at the high level, the impulse signals SP1-SP3 are generated respectively after the receivers 130_1-130_3 finish the reception. As a result, the receivers 130_1-130_4 sequentially receive the corresponding frame data at different times.
However, in the driving process 30, the receivers 130_2-130_4 are activated by the system timing generation signal SYS at time t1, but do not function until respectively triggered by the impulse signals SP1, SP2, SP3 at time t2, t3, t4, which are determined based on when the previous source drivers finish the reception. That is, in standby durations P2, P3, P4, the receivers 130_2-130_4 dissipate power without performing any functions. Therefore, the conventional driving process 30 has to be improved.